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IP technology and its industrial development characteristics in integrated circuit design

release time:2022-03-17Author source:SlkorBrowse:742


Based on the development trend of IC design industry technology, this paper discusses the related technologies of IP core and its unique development mode. Starting from the market and technology development trend at home and abroad, this paper analyzes the IP required by high-end chips supported by advanced technology and mature chips supported by characteristic technology, and briefly introduces the application of advanced design and manufacturing collaborative optimization and artificial intelligence technology in IP verification. Finally, the strategies and suggestions for developing IP technology and industry in IC design in China are put forward.


1.1  Industrial background

IC industry is the core of information technology industry, and it is a strategic, basic and leading industry to support economic and social development and ensure national security.The orientation of the three major characteristics of the industry in the National Outline for Promoting the Development of IC Industry is mainly reflected in:(1) China's annual import of integrated circuits in recent years is huge, reaching USD 260.1 billion in 2017 (the latest customs data shows that it reached USD 312.058 billion in 2018), which is much higher than the total import of crude oil or other strategic substances; (2) The development of industry is highly dependent on the support of basic industries such as materials, machinery (equipment), electronics and software; (3) Cutting-edge leading technology research and development results are usually first applied in the integrated circuit industry, thus guiding the development direction of other industries. Chips are as important as steam engines and internal combustion engines in the first and second industrial revolutions. Whether it's mobile phones and computers in daily life, servers and data centers for enterprise applications, industrial robots, or even aerospace and national defense security, chips are indispensable.

IP (intellectual property core) in chip design usually refers to reusable circuit modules with specific functions, which are applied in SoC, and have standardization and tradeability. IP circuit modules that have passed industrial verification can be directly implanted into chips by system design engineers. Including IP CPU class (including DSP, MPU, MCU), has become the core and essence of integrated circuit design technology. Generally, IP can be divided into three types: soft core, hard core and firm core.

IP core is a register transfer level (RTL) code that is independent of manufacturing process. After functional verification and optimization at behavioral level, IP core has considerable flexibility in use. IP hardcore is a semi-finished product or product obtained through system design verification, physical layout design verification and process manufacturing. Its advantage is to ensure that the circuit performance meets the design goal, and the submission form is all the layout of the mask structure of chip manufacturing and a complete set of process-related documents of the detailed system. Due to the binding with the complete process, the hard core has no flexibility in application. After the process upgrade, the corresponding hard core needs to be re-verified and re-designed physically. Between the soft core and the hard core is the IP solid core. The core is usually submitted in the form of gate-level netlist. Because the final wiring design of the solid core is mostly completed by the design customer, the port position, shape and size of the core can be adjusted, which is more flexible than that of the hard core.

A reusable IP core must have a complete description of system design and application parameters (specifications), various compatible application models, configurability, verification codes and test files, general bus interface and general detection interface, script files, design and transfer documents related to function verification, logic synthesis and physical design verification, etc.

From the product types of IP design, it can be divided into:(1)IP mature product module class. It can be directly integrated with applications, such as DDR die, also known as known good die (KGD); (2)IP semi-mature product module class, also known as verification IP (VIP for short). IP designers need to provide verification codes for the unified integration of SoC; (3) newly defined or newly developed IP(design IP, DIP) that needs to be designed. The types of VIP are: high-speed IP, such as Peripheral Component Interface Express (PCIe), rapi-dIO, etc. The types of DIP are: DIP for artificial intelligence, DIP for big data, DIP for Internet of Things (IoT), etc.

According to the integration mode and application scenario of IP core in SoC, it can also be divided into:(1) interface IP, such as universal serial bus (USB), serial advanced technology attachment (SATA), PCIe, high definition multimedia interface/display port (HDMI/DP), etc. (2) IP storage, such as static random access memory (SRAM), dynamic random access memory (DRAM), NAND/NOR flash memory, OTP/MTP memory, etc. (3) Functional IP, such as analog-to-digital converter (ADC/DAC), digital signal processor (DSP), microcontroller (MCU), audio and video interleaved (AVI), etc.

With the development of technology in integrated circuit industry, the performance and complexity of IC design are constantly improving, and the scale of many ICs has reached 10 ~10¹⁰Transistors, as shown in Figure 1, thus putting forward higher, faster and more accurate requirements for IP verification. The existing and developing verification methods have shown that the larger the design scale, the longer the verification time, and the more difficult it is to increase the verification coverage. As shown in Figure 2, this directly affects the convergence of indicators such as the performance of IP or IC products, affects the design for reliability (DFR), and indirectly affects the mass production (cost) of products, also known as designfor yield (DFY).


The relationship between the increase of 2.IC/IP design scale and complexity and verification accuracy

1.2  IP background of global chip industry

The upstream of the IC industry is design IP, and the global IP market in 2018 is about USD 4.9 billion. Although the output value of IP itself is not the highest, it has great added value and unique industrial ecological pillar function, and its products are closely related to national information security. SoC technology based on IP core reuse is the development direction of global integrated circuits. The SoC with IP core design in the industry accounts for more than 90% of the total. The top 10 design IP suppliers in the world are shown in Table 1.

Table 1. Top 10 IP Suppliers in the World in 2017

ARM, the global leading IP nuclear enterprise, increased its market share from 33% in 2007 to 46.2% in 2017, indicating that IP is developing in a highly concentrated direction. The global development path of IP is mainly driven by the rising SoC market. At the same time, the open source CPU instruction set (ISA) architecture RISC-V, the technical penetration of artificial intelligence and the interface IP promoted by the Internet of Things (IoT) are the hot trends of IP development in the future. For example, integrating a variety of traditional CPU, GPU, DSP and other modules into the design of heterogeneous system architecture (HSA) on the same chip, and the newly proposed future domain specific architecture (DSA), which is concerned by DARPA, will bring new application requirements to the development of IP.

With the development of global industry, the processor IP market will occupy the largest market share. Due to the increasing demand for microprocessors (MPU), microcontrollers (MCU), digital signal processors (DSP) and graphics processing units (GPU) in various vertical fields, processor IP will occupy the largest share of the semiconductor IP market. Among them, the IP core licensing business represented by ARM, the leading mobile communication microprocessor company, continues to show great business opportunities in recent years, especially in the post-Moore era when the chip technology develops. IP core has obviously become an amplifier in the chip design industry. The post-Moore SoC design needs more and more IP cores. From the perspective of business opportunities, the number and quality of IP cores owned by a chip manufacturing enterprise have become the core of its market competitiveness; From the perspective of national strategy, the IP cores owned by a country reflect its level of occupying the commanding heights of integrated circuit strategy, among which the high number and high quality of IP cores become the commanding heights of the chip industry. In fact, IP core has become an indispensable low-cost weapon for the IC industry to implement mass innovation.

The development of IP technology is closely related to the development of process technology. At present, the global mainstream advanced technology is the 10/7 nm complete process, and the 5 nm complete process will also enter the industrialization stage in the next three years. And the chip manufacturing technology, from the technical route with three-dimensional transistor FinFET structure as the main line, has expanded to all-round technological innovation. Its innovations are mainly in three aspects: transistor structure, material and technology, and innovation of chip structure.

With the development of 2D plane technology to 3D technology, the chip design has changed greatly.Thereby fundamentally changing the design of the chip transistor:Including 3D FinFET chip design, gateall-around (GAA), quantum tunnelingeffect, etc. After entering the 28 nm technology generation, the proportion of planar transistors has been reduced to the limit, and 3D transistors have gradually become the mainstream. It is expected that the mainstream technology will still adopt 3D FinFET architecture and immersion 193 nm(i193) lithography technology. Because of the complicated process and the inevitable increase in cost, the gate structure may be applied at the node of 5 nm at the earliest. Figure 3 shows the development roadmap of the mainstream transistor structure in the global integrated circuit industry, and the main goal of its technical development is to improve the performance-to-power ratio. At the same time, due to the market drive of the Internet of Things, the research of ultra-low power devices, such as tunnel field-effect transistor (TFET), will also be the technical development direction of integrated circuits, and the accompanying research and development of epitaxial, deposition, etching, CMP and other equipment and related materials need to be followed up. Especially lithography, the technical threshold from immersion 193 nm multiple exposure to EUV lithography has not completely crossed. EUV mask technology has encountered some bottlenecks in mass production, such as defect detection of mask and durability of pellicle, etc. The large-scale industrial application still has a hard way to go. It can be expected that in the future, the technological development speed marked only by feature size reduction will slow down, while the technological progress of power consumption and performance will become the trend of industrial technology development.

Figure 3. Development Roadmap of Mainstream Transistor Structure in Global IC Industry (provided by Academician Huang Ru)

2.Present situation of IP industry in China

At present, there is no company in China that specializes in IP hardcore design similar to that in foreign countries, and the successful design of chip design companies can't be defined as IP. There are domestic companies that provide IP soft cores, which can be provided to users in RTL format. In view of the above situation and differences, there are three main directions for the development of IP cores in China, namely, IP cores of high-end processors, IP cores of high-speed interfaces, and application IP closely related to product applications. Among them, the IP core of high-end processors is completely monopolized by foreign countries (such as ARM), and domestic products are basically in a blank state. As the high-end processor is not profitable in the short term, there is no IP company in China to carry out related research and development, and there is no development plan. As for the IP core of embedded processor, because the threshold is not as high as that of CPU, and there is a high profit margin, some domestic companies are currently conducting research and development; Class IP (such as SerDes, DDR and USB, etc.), several domestic companies have opened up a good R&D and market situation. As for application IP, it is basically developed by chip design companies and chip manufacturing companies. At the same time, as the domestic 14 nm technology generation is about to complete the process research and development, it is urgent to establish a relatively complete 14 nm IP library.

As of 2018, more than 90% of the existing 1,698 chip design enterprises in China have a turnover of less than 100 million yuan. The development of these design enterprises mainly depends on the Chinese market, but their technology accumulation is insufficient. These enterprises can't pay attention to the development of every technology link, and their limited technology R&D resources can only focus on the development of some products, which can't be fully rolled out. Especially in the use of some general IP cores, enterprises need to have the foundation of process support and design services.

Enterprises need to pay more attention to the intellectual property value of IP, especially in the current hot spot of international competition. They need to strengthen the protection of their own IP and make good use of other people's IP, so as not to put themselves in uncontrollable intellectual property risks.

Fully controllable chip design IP core technology is still one of the important factors restricting the development of integrated circuit design in China. China's IP enterprises are basically small and scattered. Although a number of IP cores have been accumulated in the past 10 years, due to the lack of technical support services and technological foundation, the utilization rate of IP cores is very low, and the existing IP lacks maintenance and gradually loses its competitiveness. The lack of perfect neutral testing system and the unwillingness of IP companies to invest in research and development make domestic chip companies have to purchase a large number of IP cores from abroad. The reason is that the IP R&D investment is large and the R&D cycle is long. For example, the IP development of 130 nm process is nearly 5 million USD, which takes about 18 months. IP R&D of 28 nm technology node needs nearly 10 million USD and about 21 months R&D cycle. This makes it difficult for domestic IP companies to carry out independent IP R&D under the support of the market, thus laying a great hidden danger for China's industrial development.

Mr. Zhu Min, an expert in IP design technology, believes that the IC industry is characterized by large investment and long return period. The current situation of IC chip industry is that a foundry for chip manufacturing (28 nm, with a monthly output of 40,000 chips) needs to invest nearly $5 billion. Most design companies don't have such a large capital investment, and it's not necessary to spend a lot of resources to run the production line, so it's the best choice to share production capacity by foundry. However, the development and application of IP have a similar situation. The development of IP on the new-generation process node (28 nm) needs to invest nearly 10 million dollars, and at least 6 months of research and development cycle. Most design companies can't invest so much resources in each generation of product design, so IP also needs to be shared. IP sharing is one of the important links to support the overall development of the industrial chain.

Therefore, it is necessary to have a common platform for IP core sharing. The public platform relies on the technological foundation of domestic chip manufacturing to provide design services for design companies. China's booming IC industry urgently needs a neutral IP public platform to provide design services. Make full use of the high-quality resources of domestic high-quality IP companies, research institutes and universities, organize a joint team in Industry-University-Research to develop IP cores, and support the innovation drive of design companies through public platforms. At the same time, it has neutral IP core test evaluation, IP core process verification and IP core related design services, including the support of public IP platform and electronic design automation (EDA) tool platform. Its structure is similar to the public platform of Design Reuse IP in France.Therefore, it is necessary to have a common platform for IP core sharing. The public platform relies on the technological foundation of domestic chip manufacturing to provide design services for design companies. China's booming IC industry urgently needs a neutral IP public platform to provide design services. Make full use of the high-quality resources of domestic high-quality IP companies, research institutes and universities, organize a joint team in Industry-University-Research to develop IP cores, and support the innovation drive of design companies through public platforms. At the same time, it has neutral IP core test evaluation, IP core process verification and IP core related design services, including the support of public IP platform and electronic design automation (EDA) tool platform. Its structure is similar to the public platform of Design Reuse IP in France.

The public IP design service platform plays the role of bridge between design enterprises and chip manufacturing enterprises. China's industry needs to build a public IP platform. Starting from the process platform construction and basic model research, we can improve the IP nuclear technology level and application scale in a down-to-earth manner. As shown in Figure 4, the architecture of public IP platform is based on the process platform, and the corresponding model, process design kit (PDK) and unit library (Library) are established, which really play a bridge connecting design and manufacturing.

Figure 4. Public IP Platform Architecture

3.IP technology development trend

Integrated circuit technology has basically followed Moore's Law for 60 years. As we enter the post-Moorish era, that is, the pace of technology replacement in two generations begins to slow down, design and manufacturing enterprises begin to pay more attention to the diversified development of products, instead of blindly pursuing the reduction of feature size, which leads to a new trend in the development of IP technology. There are six aspects of IP technology development trend.

3.1  The combination of IP technology and technology is getting closer and closer, and it is changing simultaneously.

IP is the key component of IC design and manufacturing, and its development trend is basically the same as the overall evolution trend of IC. It is developing in the direction of shrinking process and precision size, increasing product integration and improving overall performance. With the increasing correlation between process and design, DTCO (Design Technology Co-Optimization) is also derived, which can meet the requirements of new process node devices through mutual cooperation.

3.2 IP R&D follows the principles of unity, simplification and localization.

In the process of IP research and development, special attention should be paid to the fact that a single reusable IP core must be assembled before it can have the value of product design. In the process of assembly, it is very important to standardize the IP core, including defining the interface signal according to a specific name, unifying the reset mode, and agreeing the habit and style of writing code in advance. At the same time, we should obey the principle of simplification, because simple modules can be easily recognized and understood by third parties, and a module with complex functions needs to be composed of a series of modules with as simple functions as possible. Finally, it is necessary to obey the localization principle, each local module is orthogonal and independent, and the interfaces between modules need to be explicitly marked. Localized design can combine cost, function, timing and other important indicators with independent modules.

3.3 The new generation of high-speed interface IP goes hot and new products emerge.

Currently, PCIe (PCI Express) 4.0 (2017; 5.0, 2019), USB 3.2(2017), DDR/LPDDR 5(2017), HBM 2 (high bandwidth memory, HBM; V2/V3, 2016), SATA rev3, HDMI 2.1, MIPI DSI/DPI, Bluetooth 5(2016) and Ethernet(400 Gbps, 2018) are emerging. In 2018, some chip companies have launched the industry's first 56Gbps PAM4 (four-stage pulse amplification modulation) SerDes IP verified by 7 nm FinFET silicon. USB3.1 IP, a domestic IP enterprise, has already obtained the certificate from Europe, becoming one of only two IP companies in the world that have obtained this certificate.

3.4  AI algorithm accelerates IP core research and development

The development of artificial intelligence (AI) technology has brought about the transformation of computing model. On the one hand, major IP suppliers have introduced IP customized for AI or combined with AI. For example, Synopsys recently introduced the high-performance embedded visual processor IP——DesignWare EV series; On the other hand, artificial intelligence algorithms are also used in IP-related EDA tools. For example, Empyrean Mcfly launched by Huada Jiutian uses artificial intelligence algorithms to accelerate IP authentication.

3.5 The R&D application of IP presents a platform development trend.

The design platform based on complete set of process technology, IC design data as the core and IP as the core assets is becoming the core competitiveness of design companies. The main task of IP platform is to research and develop the IP urgently needed by design companies and provide corresponding design technical services, and the design verification of IP runs through the whole design process, as shown in Figure 5.

Figure 5.IP verification runs through the whole design process.

Traditional testbench is suitable for small-scale design, and it is an assertion-based verification (ABV) method. For the verification and integration of IP in the design of super-large scale SoC and mixed-signal signals, Universal Verification Methodology (UVM) based on transaction-level modeling (TLM) has been developed and applied for many years, and is becoming mature. In UVM technology, according to design characteristics and application scenarios, designers can choose different verification languages to model and verify IP design, as shown in Figure 6. For example, for small and device-based designs, SPICE language is used as the main verification; For analog IP design, Verilog-A language is adopted for verification; The design of mixed-signal IP can be verified by Verilog-AMS language. For IP design applied in very large digital circuits, it is necessary to establish TLM, adopt UVM and apply SystemVerilog language for verification.

Verification of 6.IC/IP design and its application

3.6  Open source IP will bring new opportunities and challenges to IP providers.

In the post-Moore era, product design will be more diversified, and embedded processors are expected to usher in a larger market space because of their diversity and flexibility of functions. Embedded processors generally operate in the business mode of IP core licensing, while the high licensing cost of ARM IP core will greatly increase the innovation cost of start-up chip design companies. Therefore, driven by the demand of many small and medium-sized companies, in recent years, some open-source free IP cores have begun to emerge.

At present, the most typical case is RISC-V launched by Berkeley Campus of University of California, USA, which can provide more than 40 basic instruction sets and dozens of other modular extension instructions for free. With the open source and loose berkeley software distribution (BSD) protocol, enterprises can develop and use the BSD system derived from Linux for free. Due to the rapid rise of RISC-V open source instruction set in recent years, many enterprises have joined in the design and implementation of RISC-V chips, and the corresponding open source IP will bring challenges to the existing leading IP providers. Of course, mature IP must be fully verified to ensure its reliability and reusability and avoid risks. While IP brings new opportunities, it will also face corresponding challenges.

The following two examples show that the collaborative optimization of design and manufacturing of high-end technology and the application of artificial intelligence to IP inspection are the inevitable ways for the future development of IP technology.

(1)Collaborative Optimization of Design and Manufacturing (DTCO).On the basic IP design method, with the development of technology, the critical dimension is getting smaller and smaller, and the process window is getting narrower and narrower. The independent mode of process and design leads to the process window being unable to meet the design requirements, so the relationship between design and manufacturing must be closely combined. In the design process, it is necessary to obey a series of design rules according to the requirements of the chip manufacturing process. Under the constraints of process and design rules, the layout and wiring of physical layout are crucial to the speed and signal integrity, and the area of compressed chips. On the 28 nm technology node and more advanced technology nodes, DTCO, a new concept and methodology of collaborative optimization of design and process, began to be adopted. So that enough windows can be left for the process from the beginning of design. The main content of process collaborative optimization is to consider the basic IP circuit design and process optimization together. Through the collaborative optimization of the two, the feature size of integrated circuits can be further reduced, and the market demand for chip power consumption, performance, area and cost (PPAC) can be met. There APPRY also opinions that propose the design and implementation scheme in the order of area, power consumption, performance, reliability and productivity. While giving consideration to manufacturability to the extent possible.There are two main reasons for adopting DTCO:1)It is becoming more and more challenging to achieve further miniaturization and chip performance improvement only by technology; 2) The market has a persistent demand for the miniaturization of chip feature size and the improvement of performance. For example, the traditional immersion lithography process has been difficult to meet the requirements in the case of single exposure. The further reduction of transistor size begins to affect transistor performance more and more, such as short channel effect enhancement, stress reduction, carrier capacitance increase, fluctuation increase, etc. After further reduction of the interconnect metal line in the back section, the resistance and capacitance change sharply, and these factors must be taken into account at the same time as the design.

The specific DTCO implementation is shown in Figure 7. Process collaborative optimization mainly occurs between process/device development and basic IP design. Usually, collaborative optimization is carried out between process and basic IP, and certain routing requirements and strategies are taken into account. Through optimization iteration, the process technology framework and standard unit design framework are defined to realize the optimal PPAC. A perfect collaborative optimization process of design process will also take into account manufacturability while achieving PPAC goals, so that competitive chip products can be mass-produced and put on the market in the fastest time.

Figure 7. Schematic diagram of 7.DTCO process

(2)IP verification adopts artificial intelligence technology.Hundreds of IP unit modules are commonly used in modern SoC design. The performance of these IPs and the quality of data delivered by their IP libraries are important factors that affect the chip performance and the whole design cycle. The design company needs to conduct in-depth performance analysis and comparison of IP libraries, detailed quality verification of deliverables and data verification before it can determine a set of high-quality IP libraries and corresponding design rules that are suitable for the design requirements. There are IP deliverables verification solutions in the industry, which can verify the correctness and consistency of IP data. In addition, in recent years, the development of artificial intelligence technology has greatly promoted IP technology. In the process of IP timing verification, machine learning can check IP. For example, Empyrean ALPS-GT, a circuit simulator of heterogeneous computing platform based on CPU-GPU heterogeneous platform architecture, is more than one order of magnitude faster than the traditional analog circuit simulator, which can greatly improve the verification efficiency of analog IP. Use artificial intelligence technology to verify IP quality, learn the previous simulated IP situation by artificial intelligence method, train a model, and let AI serve IP quality verification.

Take the nine-day Timing ARC verification of Huada as an example. TimingARC is the most critical and basic component element in time series calculation. If there is a causal relationship between the pins of the IP unit in time sequence, it is called Timing ARC. Traditional inspection methods have great limitations in verifying the Timing ARC function of IP. This is because the rule- based method cannot support the functional verification of MissingARC. With the increasing scale of IP, an IP has hundreds or even thousands of inputs and outputs, and millions of ARCs need to be verified. Obviously, this can't be met by the traditional simulation test methods in time and resources. Even the internationally famous large IC design enterprises spend a lot of human resources (dozens of people) and time (several months) to complete IP verification perfectly.

With the help of machine learning (ML) technology of artificial intelligence, designers can quickly and accurately check the timing problems such as Missing Arc Validation for IP design. The process is shown in Figure 8. In an application example, the IP to be analyzed includes PLL, TX, RX, PHY, LDO, HBM, etc. The training set is 30 IPs of 16 nm process, and the test set is IP designed by 7 nm process. The training time is about 1 hour, and the timing verification of tens of millions of Timing ARC can be predicted within 10 minutes. 

Figure 8. Schematic diagram of IP timing verification using AI-ML technology (provided by Huada Jiutian)

4.Strategies and suggestions for developing China's IP industry

It can be predicted that the development of integrated circuit industry in China will be quite rapid in the future. The top level of IC industry is designing IP core, so our country must have full current understanding and forward-looking plan for developing IP core. The basic strategy to rapidly improve China's IP level is as follows: we need to firmly realize that we must resolutely take the road of independent innovation and give priority to the layout of core IP; Relying on the elite team, focus on breaking through key IP; Take conventional IP as the starting point and mature technology as the foundation, and vigorously build a public IP platform to support the healthy development of the industry.

(1)Resolutely take the road of independent innovation and give priority to the layout of core IP.On the one hand, the importance of IP is reflected in that it is located at the highest end of IC value chain, with high added value and huge ecological support; On the other hand, its products are often used in key areas involving national security issues. At present, China's international situation is becoming increasingly complicated. In the field of chip products related to national security, we must set a long-term goal and adhere to independent, controllable, safe and reliable development. After more than 20 years of development, China has initially established the foundation for independent innovation of core IP, and the core architecture IP field has gradually deepened, and market innovation IP products such as Internet of Things (IoT) and artificial intelligence have emerged one after another. On the one hand, we should continue to play the role of research institutes and leading enterprises as the main force, stimulate their enthusiasm for technological innovation, and intensify independent innovation; On the other hand, it is necessary to further develop some markets, apply the high-end technologies of innovative enterprises to the key core areas of the country, and give full play to their role as a "new force".

(2)Relying on the elite team, we will focus on the breakthrough of key IP core R&D and application.IP is the embodiment of product competitiveness in a field, the bottleneck of a certain kind of product or technology, and the turning point from low-end to high-end. At present, the most advanced high-speed serial interface SerDes, high-speed ADC/DAC and other key IP are still in the hands of a few leading enterprises such as Broadcom, ADI and TI. Due to the complexity and variety of technologies, it is impossible for integrated IP providers like Synopsys to acquire a large number of key IP through purchase. Each key IP usually has independent technical points and strong technology, and the key lies in whether a truly professional technical team with industrial and product background can be found to develop and implement it. Therefore, to break through the key IP, we should rely on professional elites and organize teams to tackle key problems. This kind of team can make a breakthrough in a key IP field in 3 ~ 5 years.

(3)Take conventional IP as the starting point and mature technology as the foundation, and vigorously build a public IP platform to support the healthy development of the industry.After years of development, China's mature technology development has a certain foundation. Conventional IP already has strong market resources and technical reserves, especially some IP with long product life cycle technology nodes. For example, IP based on 55 nm and 28 nm complete sets of processes can rely on the existing mature manufacturing processes, aiming at a large quantity and wide range of products (such as MCP, etc.) and rely on market competition for development. For this kind of IP, the government doesn't need to invest a lot, but only needs to create a good environment for market competition and industrial development. Therefore, we can build a public service platform to support the development of conventional IP, encourage experienced people to develop IP, open up IP transaction application channels, and make technological breakthroughs through market competition.

To sum up, the development of IP field in China's IC industry has made great progress, and at the same time, there is a significant gap with the mainstream of the world. In the process of catching up, the following five suggestions are put forward.

(1)Form enterprise alliance to form joint force.Promote the establishment of patent sharing alliances in large industries, keep warm, jointly overcome patent barriers, and resist international patent attacks. Through independent creation, corporate mergers and acquisitions and overseas patent acquisitions, we can increase the accumulation of intellectual property rights of enterprises, and at the same time, build a patent sharing community by means of industrial alliances and interest alliances. Support the construction of public IP platform. It is suggested to set up professional funds for professional mergers and acquisitions to enhance comprehensive competitiveness.

(2)Increase the protection of intellectual property rights。Simplify the identification method of direct and indirect economic losses of IP infringement, shift from compensation for direct and indirect economic losses to relatively severe punitive clauses of IP infringement, and gradually become stricter in judicial interpretation and practice to crack down on piracy and infringement. Make full use of China's industrial chain and market advantages in the global division of labor, and take some effective judicial measures against overseas litigation. Set up corresponding patent operating companies, refer to the international commercial patent operating company model, and jointly resist foreign patent litigation.

(3)Build a differentiated investment system.It is suggested to construct a multi-level and all-round investment structure composed of national industrial funds, local funds and other social funds, and provide investment and industrial services for enterprises of different sizes, so as to solve the current situation that IP enterprises need investment and worry that large investment will affect the company's equity and management mode. It is also possible to set up various types of sub-funds to invest in IP enterprises with relatively small amount and certain risks, but with positive significance to the industry.

(4)Multi-channel fiscal and taxation and investment and financing support.Increase financial policy support for IP nuclear design, introduce corresponding tax relief policies, establish fund projects specifically for IP nuclear research and development, and adopt the "platform+project" operation mode to encourage and guide the development of new IP nuclear products. Give investment and financing support, growth incentives and policy support to IP nuclear design and R&D projects, and guide relevant enterprises to concentrate their R&D efforts to break through the key IP nuclear fields urgently needed in China.

(5)Intensify efforts to cultivate talents.Attach importance to the cultivation of relevant professionals, support the construction of demonstration microelectronics colleges, increase relevant professional courses and scientific research projects in colleges and universities, introduce experienced engineers and technicians to teach relevant technical courses in colleges and universities, promote Industry-University-Research's multi-party connection, realize collaborative innovation in the form of industrial alliance, and promote the development of domestic IP nuclear industry. Encourage enterprises to carry out school-enterprise cooperation in educating people, and form an integrated training chain from student training to enterprise internship and employment. Introduce high-end talents with rich front-line work experience to form teams and cultivate young talents.


This paper discusses the development trend of IP nuclear technology in China from the attributes and technical characteristics of IP, combined with the current situation of technology and industry at home and abroad. In view of our catching-up development road, we put forward five corresponding suggestions. For readers' reference. I hope you can criticize and correct me if something is wrong.

Disclaimer: This article is reproduced from "Semiconductor Industry Watch". This article only represents the author's personal views, and does not represent the views of Sacco Micro and the industry. It is only for reprinting and sharing to support the protection of intellectual property rights. Please indicate the original source and author when reprinting. If there is any infringement, please contact us to delete it.

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