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Everything About Intel's Advanced Packaging Technology (Part II)

release time:2024-01-31Author source:SlkorBrowse:3307

Continued from "Everything About Intel's Advanced Packaging Technology (Part I)" 

Next, I will share the content on the scalability axis (Z) which is represented by the Z-axis in Figure 1. Co-EMIB technology is located within this quadrant. Co-EMIB technology combines 2D and 3D technologies using a combination of EMIB and Foveros to achieve scalability. With Co-EMIB, we can place over 40 chips into a single package.

The Co-EMIB architecture is based on high-density connections between companion chips and stacked chips, enabling a wider range of interconnectivity. The figure below shows that HBM can be placed together with Foveros or there can be different companion chips.

There is another technology on the scalability axis (Z) called Omni-Directional Interconnect (ODI), which represents a new dimension in advanced packaging. The figure below shows Intel's Foveros technology on the left, where we stack chips and use TSVs to communicate between the chip and substrate, as well as between chips, all the way up to the top chip. On the far right of the figure, we have added metal pillars, allowing the top chip on the far right to be directly connected to the package.

This is very helpful for us because it can reduce the number of TSVs at the bottom chip, which provides us with the ability to directly power the top chip. This is another optimization that allows for comprehensive customization for customers through the addition of ODI technology. Above is the research and development plan as well as the latest research results in the field of advanced packaging shared by Intel.

Thank you very much for the wonderful sharing from Academician Johanna Swan. I personally feel very benefited, and I believe the readers will have a similar experience. Through the technology sharing from Intel, I have gained a deeper understanding of technologies such as EMIB, Foveros, Chiplet, Co-EMIB, and ODI, and further learned about Hybrid Bonding and Self-Assembly technologies. Next, I would like to ask Academician Swan about some hot topics.

Chiplets, which we also refer to as tiles, are important for packaging interconnects, as they allow us to obtain small independent IPs. Once we have independent IPs, we can mix them in many products with very high reusability. We can deeply customize products integrated into packaging according to our needs. I believe customization is the real reason for achieving the next stage of heterogeneous integration. Therefore, obtaining IPs from different process nodes and integrating them heterogeneously into different processes or nodes can enable deep customization for customers.

Currently, the bonding method from wafer to wafer (WoW) is under development. How is Intel positioning itself in this bonding method?

Wafer-to-wafer (WoW) bonding technology is indeed under development. When considering the interconnection of products, there are currently two methods: wafer-to-wafer (WoW) and chip-to-wafer (CoW) bonding technologies. I believe both wafer-to-wafer (WoW) and chip-to-wafer (CoW) bonding technologies are important, depending on your product. For example, for memory stacking, we can see industry players using wafer-to-wafer bonding today. The industry is also working on chip-to-wafer bonding, which presents some unique challenges different from wafer-to-wafer bonding, but both are important. In addition, Hybrid Bonding technology can be applied to both wafer-to-wafer (WoW) and chip-to-wafer (CoW) bonding technologies.

Where do 2.5D and 3D integration technologies currently stand? The market currently presents a combination of 2.5D and 3D packaging. How does Intel view this trend?

2.5D and 3D integration technologies are developing rapidly, and I believe this trend will continue. Moreover, the opportunities and differentiation advantages brought to products by this trend are crucial. Intel's Co-EMIB is a technology similar to the combination of 2.5D and 3D, which makes products like Intel's Ponte Vecchio possible. Ultimately, our opportunity is to provide the most units per cubic millimeter and achieve the most functionality per cubic millimeter. Advanced packaging will continue to miniaturize and shrink in size so that we can achieve the maximum functionality per cubic millimeter.

There are also many semiconductor packaging and testing companies in China, and their market share is gradually expanding. However, the level of technological advancement currently does not reach the level of Intel and Samsung. What is the reason for Intel's leading position in packaging and testing technology? How do you think China's packaging and testing technology research and development can be improved?

In general, the key to recognizing the differentiation factor in packaging is the customer. We have always been striving to serve our customers and provide unique solutions to them, which has also driven the advanced packaging technologies we are focusing on. So I believe the opportunity lies in the fact that as we continue to serve our customers, their product needs are also evolving, which is the real reason driving the need for a transformation in packaging. I believe the answer to this question is that technology will come, and these technological advances will appear as our customers' differentiated needs evolve. Therefore, seizing this opportunity will be beneficial for improving packaging and testing technology research and development.

In the past, semiconductor manufacturing companies and semiconductor packaging were separate. Now, many chip manufacturing plants are trying to develop semiconductor packaging and testing technologies. Therefore, I would like to know your predictions for the future trends of semiconductor manufacturing and semiconductor packaging testing. Will they merge or develop into a coexisting mode?

This is a very good question! This is exactly what makes advanced packaging exciting. Because when we talk about 10-micron hybrid bonding, we see that these two worlds are merging. I have begun to study the characteristics of metal layers we are using, which have feature sizes below 10 microns, for example, 4 microns. Now, the feature sizes for on-wafer metal interconnects and the feature sizes we are creating when putting these chips together as part of the packaging are quite consistent. So chip manufacturing and packaging testing are merging, as the process sizes are similar, which has become a very important and interesting place for innovation. Traditional wafer fabs are using packaging and testing technologies and creating a brand new area in advanced packaging. I believe semiconductor manufacturing and packaging testing will gradually come together.

In the IDM 2.0 strategy, what role does advanced packaging play? Will Intel's advanced packaging technologies be fully opened to future foundry businesses? What are Intel's plans for advanced packaging after IDM 2.0?

I believe the first part of the question regarding the role of advanced packaging in IDM 2.0 is that it will play a very important role because it is a crucial differentiating factor. We will have many customers with different requirements, and advanced packaging will help us customize according to these requirements, making it a very critical aspect. It can be assured that customers of Intel's foundries will be able to use our cutting-edge technologies. We will offer advanced packaging technologies that have already been developed, including 2D, 2.5D, and 3D, and provide these technologies to our foundry customers to meet their unique needs. Obtaining these technologies is very important for customers to meet their specific product requirements, and these technologies can also be extended to meet higher-level requirements.

In the current fan-out packaging market, there are two technical routes, namely FOWLP and FOPLP. We all know that Samsung is developing FOPLP. I would like to know if Intel has any plans for the FOPLP route?

I want to say that it's because quantity drives demand. Your question is whether there is wafer-level packaging and panel-level packaging, and whether Intel plans to move towards panel-level packaging. Intel has been actively involved in the Fan-Out packaging plan for many years, and we will continue to evaluate whether demand will prompt us to consider FOPLP-type packaging. Intel currently has the capability to do this, and it mainly depends on whether the market conditions want us to shift from wafers to panels. This is a question we must answer, and I believe such questions will continue to arise. We will continue to actively research and develop in this field, and it is important to push for feature size improvements in any type of packaging technology, whether it is done on wafers or panels; I believe the market will make the decision for us.

Moores Law is gradually fading, and SiP packaging technology is proposed as a new breakthrough in semiconductor packaging. CPUs and FPGAs in servers also require high-end SiP. How does Intel view SiP packaging technology? Will Intel lay out in this area? Furthermore, can Intel's EMIB, CO-EMIB, and Foveros technologies be considered system-level packaging technologies?

I believe system-in-package (SiP) integration will definitely continue. SiP technology includes the architectures of 2D, 2.5D, and 3D. Sometimes people think system-level packaging is part of 3D heterogeneous integration, but in reality, it is not only that. System-level packaging emphasizes the effectiveness of the system. EMIB, CO-EMIB, and Foveros technologies all contribute to forming part of the system-level packaging. System-level packaging emphasizes the implementation of the system within the package. When we create Curie modules, we implement the system within the package. System-in-package integration can include many different things and complete the functionality of the system. Clearly, 2D, 2.5D, and 3D are all potential implementation methods for system-level packaging.

When it comes to the layout of advanced packaging, wafer foundries, IDMs, fabless companies, EDA tool vendors, etc., have all joined in. Will there be significant differences in the understanding of "advanced packaging" among these different types of companies? Is there a clear boundary between advanced packaging and traditional packaging?

From traditional packaging to advanced packaging, is it a continuum or is there a clear boundary? I believe the term "advanced packaging" signifies that it is a continuum of technological progress. I am not sure if there is a clear distinction between advanced packaging and traditional packaging. The reason why there is the term advanced packaging is that we need to stack chips and interconnect them, which is a new requirement for EDA tools, rather than traditionally placing chips on organic packaging, which is what traditional EDA tools need to handle. Now we have additional layers, an additional 3D dimension, and we need to optimize on this basis. We are faced with the fact that as advanced packaging continues to evolve, our EDA tools will become more complex and require the entire ecosystem to bring everything together and optimize, and bring us better performance.

In my new book "Microsystems based on SiP Technology," I propose a new concept: the Function Density Law, which evaluates the development of electronic systems based on the number of functional units (Function UNITs) per unit volume. It shifts the judgment standard from Moore's law on the wafer plane to the space of electronic systems, evaluating the integration degree of electronic systems from a three-dimensional perspective. How do you view this?

If you are asking about the concept of measuring the integration level of electronic systems from a 3D perspective, I think this is a very good way to quantify the concept you have provided. I believe our opportunity lies in providing more functionality per cubic millimeter to engineers and new technologies. So, I really like your proposed concept. We know there is a three-dimensional space, and we can start exploring more in the three-dimensional space. I think this is a way of thinking, and I really appreciate this kind of thinking.

The main functions of traditional packaging are chip protection, scale expansion, and electrical connection. On top of these, advanced packaging adds a few functions and features. My understanding is that increasing function density, shortening interconnection length, and conducting system restructuring are three important new features of advanced packaging. How do you view this?

I understand the points you mentioned, and what interests me is what the term "system restructuring" means. In this era of heterogeneity, when we adopt different process flows and recombine chips, system restructuring refers to how to recombine chips to minimize area overhead, power consumption, and achieve good thermal performance. Therefore, my understanding is that system restructuring means how to recombine chips and obtain optimal performance, minimal area overhead, and low power consumption. Through system restructuring, we can better recombine chips from different process nodes, minimizing the required overhead and achieving more functionality per cubic millimeter.

When we talk about heterogeneous computing, are we referring to the differentiation of CPU, GPU, FPGA, and other architectures, or are we referring to the use of heterogeneous integration to form advanced packaging?

I am not sure if I can make a clear distinction. It is precisely because we are combining these different process nodes to drive this continuous unity that we call it packaging. Therefore, they are together, and we have not really decoupled them. To achieve this, all these different process optimizations and collaborations are driving our advanced packaging and creating this heterogeneous integration.

Does Intel's Hybrid Bonding technology and other advanced integrated packaging technologies currently have limitations? How will these be addressed in the future?

There are different ways to conduct Hybrid Bonding, including wafer-to-wafer WoW and chip-to-wafer CoW. Overall, the industry is still working to improve the maturity of the technology for mass production. Industry efforts are needed to drive chip-to-wafer Hybrid Bonding to achieve mass production. This is the stage where our industry is at. Another key aspect is cleanliness. Undoubtedly, Hybrid Bonding is a physical technology, and during the bonding process, high cleanliness must be maintained. We are doing this at room temperature, which is an advantage of Hybrid Bonding. However, it must be kept very, very clean, which is different from the cleanliness required in traditional packaging. Attention must be paid to cleanliness issues when adopting these advanced packaging technologies.

Do you believe that new packaging situations will emerge in the future?

I think it will be extreme heterogeneous integration. I believe that advanced packaging technologies will continue to minimize feature sizes. As I described earlier, bringing small independent IPs together in the form of chiplets is the direction of advanced packaging development. Extreme heterogeneous integration is the future trend of advanced packaging technologies.

In conclusion,

Through in-depth communication and exchange with Intel Academician Johanna Swan, we can draw the following conclusions:

In the future of advanced packaging, the density of interconnections will increase, the pitch between protrusions for interconnecting interfaces will shrink to below 10um, and the number of protrusions per square millimeter will exceed 10,000.

Hybrid Bonding technology is widely used in high-density advanced packaging. In Hybrid Bonding, there are no protrusions, and besides metal bonding, silicon bodies bond together. There are no gaps between silicon chips and no need for filling glue. It also has better heat dissipation performance because silicon itself is a good thermal conductor. Additionally, Intel's Hybrid Bonding technology and TSMC-SoIC technology have striking similarities.

From Intel's technology roadmap, we can see that advanced packaging will not only move towards higher density but also focus on the flexibility of integration. Co-EMIB and ODI embody this characteristic.

From SoC to SiP and then to chiplets, electronic integration increasingly focuses on high efficiency, low defect rates, and high reusability.

Intel's pursuit of maximizing functionality per cubic millimeter aligns with the concept described as the Function Density Law in my new book, which evaluates the amount of functionality per unit volume. This similarity confirms the correctness of the Function Density Law.

Integrated circuit manufacturing and packaging testing are gradually merging, including both production and design aspects, bringing challenges and more opportunities for collaboration.

Extreme heterogeneous integration remains the direction and future trend of advanced packaging.

Finally, on behalf of myself and the readers, I express my gratitude to Intel and Academician Swan! I hope to have the opportunity for further communication and learning in the future.

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